1. Field of the Invention
The present invention relates generally to the field of processors, and specifically, to a method and micro-architectural apparatus for prefetching data into cache.
2. Background Information
The use of a cache memory with a processor is well known in the computer art. A primary purpose of utilizing cache memory is to bring the data closer to the processor in order for the processor to operate on that data. It is generally understood that memory devices closer to the processor operate faster than memory devices farther away on the data path from the processor. However, there is a cost trade-off in utilizing faster memory devices. The faster the data access, the higher the cost to store a bit of data. Accordingly, a cache memory tends to be much smaller in storage capacity than main memory, but is faster in accessing the data.
A computer system may utilize one or more levels of cache memory. Allocation and de-allocation schemes implemented for the cache for various known computer systems are generally similar in practice. That is, data that is required by the processor is cached in the cache memory (or memories). If a cache miss occurs, then an allocation is made at the entry indexed by the access. The access can be for loading data to the processor or storing data from the processor to memory. The cached information is retained by the cache memory until it is no longer needed, made invalid or replaced by other data, in which instances the cache entry is de-allocated.
In a computer system having multiple levels of cache, the processor typically checks in a next lower level (e.g., a second level) cache for data on a load xe2x80x9cmissxe2x80x9d to a higher level (e.g., a first level) cache. If the data is not in the lowest level cache, then the data is retrieved from external memory. This xe2x80x9cdaisy-chainxe2x80x9d or xe2x80x9cserialxe2x80x9d data lookup mechanism decreases system performance (by wasting clock cycles) if it is known or there is a high likelihood that the data is not in the lower level(s) of the cache.
Accordingly, there is a need in the technology for a method and apparatus to allow the flexibility to retrieve data from external memory and bypass the second level cache upon first level cache xe2x80x9cmissxe2x80x9d.
It is further desirable to provide a method and apparatus to place the data in a first level cache while prefetching data exclusively into a second level cache, based on external conditions.
In one embodiment, the present invention is a computer system. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss.